1. Field of the Disclosure
The instant disclosure relates to a voltage level shifter; in particular, to a voltage level shifter with 8 transistors (8T).
2. Description of Related Art
Referring to FIG. 1, FIG. 1 shows a circuit diagram of a traditional voltage level shifter in prior art according to an embodiment of the instant disclosure; a traditional voltage level shifter 100 includes N N-type transistor M1 and M2, and P-type transistors M3-M6. A gate of the N-type transistor M1 receives an input voltage IN; a source of the N-type transistor M1 is connected to a ground voltage GND′. A gate of the N-type transistor M2 receives an input voltage INN; a source of the N-type transistor is connected to a ground voltage GND′. A gate of the P-type transistor M3 is connected to a drain of the N-type transistor M2; a drain of the P-type transistor M3 is connected to a drain of the N-type transistor M1 and outputs an output voltage OUTN. A gate of the P-type transistor M4 is connected to a drain of the N-type transistor M1; a drain of the P-type transistor M4 is connected to a drain of the N-type transistor M2 and outputs an output voltage OUT. A gate of the P-type transistor M5 receives a bias voltage VP′ to bias voltage at a linear region; a drain of the P-type transistor M5 is connected to a source of the P-type transistor M3, and a source of the P-type transistor M5 is connected to a system voltage VDD′. A gate of the P-type transistor M6 receives the bias voltage VP′ to bias voltage at the linear region, and a drain of the P-type transistor M6 is connected to a source of the P-type transistor M4; a source of the P-type transistor M6 is connected to the system voltage VDD′. It is to be clarified that the two input voltages IN and INN are anti-phase.
Regarding the traditional voltage level shifter with a structure of 6 transistors, when the N-type transistor M1 is opened and the N-type transistor M2 is closed, an output voltage OUTN transited to a ground voltage GND′ will have the P-type transistor M4 opened to bring an output voltage OUT to the system voltage VDD′. Nevertheless, since only going through or passing the P-type transistor M6 that the output voltage OUT is increased to the system voltage VDD′, there could be a problem of a long-time transition.